Senior Engineer Functional Verification and Methodology

Are you ready to be at the forefront of innovation and efficiency? As a Senior Engineer Functional Verification and Methodology, you will ensure the most efficient development of Infineon products with right quality, delivered with first time success. You will play a crucial role in Infineon's value creation chain, contributing directly to product development and focusing on efficient execution, maintenance, and continuous improvement.

Job Description
As a Senior Engineer Functional Verification, you will have the opportunity to create and define verification plans, develop verification environments using UVM, and utilize System Verilog for test scenario creation and functional verification. Your expertise will be crucial in interacting with cross-disciplinary teams, providing proactive support, and ensuring the robustness of our verification methods.

In your new role you will:

• Create and define verification plans
• Develop verification environments for our ICs using Universal Verification Methodology (UVM)
• Create test scenarios using System Verilog
• Verify functionality using the Constrained Random approach
• Develop assertions in System Verilog for formal verification
• Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies
• Provide proactive support to users of our verification flow environment
• Be responsible for our verification methods

Your Profile
You are a team player with a keen eye for detecting and addressing intricate nuances in your work. Problem-solving is at the core of what you do, and you thrive in identifying and resolving complex challenges that arise during the verification process. You are an expert with prioritization, demonstrating an ability to allocate time and resources effectively to meet project deadlines and deliverables.

You are best equipped for this task if you have:

• A university degree in Electrical Engineering, Computer Science or a similar academic discipline
• At least 3 years of experience in Constrained-Random Metric Driven Verification
• Experience working with microcontroller-based ICs, as well as security and safety requirements
• Good know-how with UVM especially using System Verilog
• Knowledge of firmware and RTL design (VHDL)
• Experience working with Verification IPs (VIPs)
• Experience with Ethernet Protocol
• C modeling experience is a plus

Please send us your CV in English
Contact:
Francisca Dias, LinkedIn

#WeAreIn for driving decarbonization and digitalization.
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

Are you in?
The central R&D organization
"Design Enabling and Services" (DES)
provides the design environments (design-systems) to the different product development teams at Infineon. With leading edge design methods, complex building blocks and a wide range of product development services DES enables Infineon's advanced IC development. This means the complete value creation chain from abstract system models down to the fully verified product layout which ensures high quality manufacturing readiness.

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